The present invention relates to a comparator circuit for comparing a plurality of input voltages and performing an output that is in accordance with the comparison.
A comparator circuit compares a plurality of input signals and outputs a signal that is in accordance with the comparison. The output signal may be in correspondence with the operation status of a circuit incorporating the comparator circuit. For example, when a circuit is entirely in a standby state, the comparator circuit may output a low level signal In this case, the circuit is not in an operational state. Thus, it is desirable that current consumption be reduced. Accordingly, measures are taken to reduce current consumption in the comparator circuit, which is part of the circuit.
Japanese Laid-Open Patent Publication No. 8-78975, FIG. 1, describes a comparator circuit including a differential amplifier, a current amplifier, a constant current circuit, and a constant current control circuit. The differential amplifier compares two input signals to amplify and output the voltage difference of the input signals. The current amplifier amplifies the current of the differential amplifier output. The constant current circuit supplies constant current to the differential amplifier and the current amplifier. The constant current control circuit detects the output of the differential amplifier and controls the constant current circuit. Further, the constant current control circuit includes a switch circuit, which is operated in accordance with low level and high level outputs, and a switch control circuit for controlling the switch circuit. In the comparator circuit, the switch circuit is activated and deactivated to change the amount of current that flows through the constant current circuit. Thus, glitches may be generated when switching is performed with the switch circuit, that is, when switching the output of the comparator circuit.
Japanese Laid-Open Patent Publication No. 2002-217691, FIG. 1, describes a comparator circuit for comparing input voltage and a reference voltage. The comparator circuit, which is activated when supplied with bias current, includes a bias enforcement circuit for adding bias current and outputting bias enforcement current. The comparator circuit outputs current that is in accordance with the state of the current from the bias enforcement circuit. Accordingly, the comparator circuit differs from that of Japanese Laid-Open Patent Publication No. 8-78975 in that the generation of glitches is suppressed.
The comparator circuit described in Japanese Laid-Open Patent Publication No. 8-78975 is configured so that current does not flow to the differential amplifier in a low current consumption mode. However, this results in the necessity to increase the current that flows to the constant current control circuit. It is thus difficult to suppress current consumption in the entire comparator circuit.
In the comparator circuit described in Japanese Laid-Open Patent Publication No. 2002-217691, the bias enforcement circuit, which monitors the current state, is constantly supplied with current. Thus, in a low current consumption mode, the reduction in current consumption is insufficient.